1. Field of the Invention
The present invention relates generally to digital processors and, more particularly, to the instruction issuing and execution units of a digital processor.
2. Description of the Relevant Art
A primary goal in the design of digital processors is to increase the throughput, i.e., the number of instructions processed per unit time, of the processor. One approach has been to improve the hardware design of the processor to reduce the machine cycle time. Another approach has been to develop architectures and instruction sets designed to process one instruction per machine cycle. Both of these approaches are limited to a theoretical maximum throughput of one instruction per machine cycle due to basic policy of sequentially issuing at most one instruction per cycle.
Systems for issuing more than one instruction per cycle are described in a paper by Ditzel et al. entitled "The Hardware Architecture of the CRISP Microprocessor", 1098 ACM 0084-7495 87, pp. 309-319 and in a paper by Acosta et al. entitled "An instruction issuing Approach to Enhancing Performance in Multiple Functional Unit Processors", IEEE Transactions on Computers, Vol. C-35, No. 9. September 86, pp. 815-828.
One limitation on concurrent issuing of instructions is that the instructions must not require the use of the same functional unit of the processor during the same machine cycle. This limitation is related to the resources included in the processor architecture and can be somewhat obviated by providing additional copies of heavily used functional units.
The paper by Acosta et al. presents an approach to concurrently issuing instructions to take advantage of the existence of multiple functional units. Further, the CRISP architecture, described in the above-referenced paper, allows the execution of a branch instruction concurrently with another instruction. Additionally, mainframes have allowed concurrent dispatching of integer and floating point instructions to different functional units.
However, all of these systems require that the instructions issued concurrently not be dependent on each other. Types of dependencies will be discussed fully below, but a fundamental dependency between a pair of instructions is that the second instruction in the pair processes data resulting from the execution of the first instruction in the pair. Accordingly, the first instruction must be processed prior to the second.
Thus, these existing processors may concurrently issue and execute very few combinations of instructions. A branch instruction is a special case where no memory reference is required and requires only that a new address be calculated. Similarly, floating point and integer instructions require only ALU resources and no memory reference. Thus, data dependencies between the instructions do not exist.
In view of the above limitations, the type of instructions that may be concurrently issued in these systems is extremely limited and, although in certain limited situations two instructions may be issued in one clock, the average throughput cannot significantly exceed one clock per instruction.